Pre-Production
WM8904
Figure 59 Clocking Overview
SYSCLK CONTROL
The SYSCLK_SRC bit is used to select the source for SYSCLK. The source may be either the MCLK
input or the FLL output. The MCLK input can be inverted or non-inverted, as selected by the
MCLK_INV bit. The selected source may also be adjusted by the MCLK_DIV divider to generate
SYSCLK. These register fields are described in Table 61. See “Frequency Locked Loop (FLL)” for
more details of the Frequency Locked Loop clock generator.
The SYSCLK signal is enabled by register bit CLK_SYS_ENA. This bit should be set to 0 when
reconfiguring clock sources. It is not recommended to change SYSCLK_SRC while the
CLK_SYS_ENA bit is set.
PP, Rev 3.3, September 2012
103
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