WM8904
Pre-Production
In FLL Fractional Mode, the fractional portion of the N.K multiplier is held in the FLL_K register field.
This field is coded as a fixed point quantity, where the MSB has a weighting of 0.5. Note that, if
desired, the value of this field may be calculated by multiplying K by 216 and treating FLL_K as an
integer value, as illustrated in the following example:
If N.K = 8.192, then K = 0.192
Multiplying K by 216 gives 0.192 x 65536 = 12582.912 (decimal)
Apply rounding to the nearest integer = 12583 (decimal) = 3127 (hex)
For best performance, FLL Fractional Mode should always be used. Therefore, if the calculations
yield an integer value of N.K, then it is recommended to adjust FLL_OUTDIV in order to obtain a non-
integer value of N.K. Care must always be taken to ensure that the FLL operating frequency, FVCO, is
within its recommended limits of 90-100 MHz.
The register fields that control the FLL are described in Table 71. Example settings for a variety of
reference frequencies and output frequencies are shown in Table 73.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R116 (74h)
FLL Fractional enable
2
FLL_FRACN_E
NA
0
FLL Control 1
0 = Integer Mode
1 = Fractional Mode
Fractional Mode
(FLL_FRACN_ENA=1) is
recommended in all cases
FLL Oscillator enable
0 = Disabled
1
FLL_OSC_ENA
0
1 = Enabled
FLL_OSC_ENA must be enabled
before enabling FLL_ENA.
Note that this field is required for free-
running FLL modes only.
FLL Enable
0 = Disabled
1 = Enabled
0
FLL_ENA
0
FLL_OSC_ENA must be enabled
before enabling FLL_ENA.
R117 (75h)
FLL FOUT clock divider
00_0000 = Reserved
00_0001 = Reserved
00_0010 = Reserved
00_0011 = 4
13:8
FLL_OUTDIV
[5:0]
00_0000
FLL Control 2
00_0100 = 5
00_0101 = 6
…
11_1110 = 63
11_1111 = 64
(FOUT = FVCO / FLL_OUTDIV)
PP, Rev 3.3, September 2012
110
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
