Pre-Production
WM8904
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Frequency of the FLL control block
6:4
FLL_CTRL_RAT
E [2:0]
000
000 = FVCO / 1 (Recommended
value)
001 = FVCO / 2
010 = FVCO / 3
011 = FVCO / 4
100 = FVCO / 5
101 = FVCO / 6
110 = FVCO / 7
111 = FVCO / 8
Recommended that these are not
changed from default.
F
VCO clock divider
2:0
FLL_FRATIO
[2:0]
111
000 = divide by 1
001 = divide by 2
010 = divide by 4
011 = divide by 8
1XX = divide by 16
000 recommended for FREF > 1MHz
100 recommended for FREF < 64kHz
Fractional multiply for FREF
(MSB = 0.5)
R118 (76h)
15:0
14:5
3:0
FLL_K [15:0]
FLL_N [9:0]
0000h
177h
0h
FLL Control 3
R119 (77h)
Integer multiply for FREF
(LSB = 1)
FLL Control 4
Gain applied to error
0000 = x 1 (Recommended value)
0001 = x 2
FLL_GAIN [3:0]
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1000 = x 256
Recommended that these are not
changed from default.
R120 (78h)
FLL Clock Reference Divider
00 = MCLK / 1
4:3
FLL_CLK_REF_
DIV [1:0]
00
FLL Control 5
01 = MCLK / 2
10 = MCLK / 4
11 = MCLK / 8
MCLK (or other input reference) must
be divided down to <=13.5MHz.
For lower power operation, the
reference clock can be divided down
further if desired.
PP, Rev 3.3, September 2012
111
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
