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WM8904CGEFL/V 参数 Datasheet PDF下载

WM8904CGEFL/V图片预览
型号: WM8904CGEFL/V
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗编解码器用于便携式音频应用 [Ultra Low Power CODEC for Portable Audio Applications]
分类和应用: 解码器编解码器电信集成电路便携式PC
文件页数/大小: 188 页 / 1824 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Pre-Production  
WM8904  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R27 (1Bh)  
Audio Interface LRC Direction  
0 = LRC is input  
11  
LRCLK_DIR  
0
Audio  
Interface 3  
1 = LRC is output  
LRC Rate (Master Mode)  
10:0  
LRCLK_RATE  
[10:0]  
000_0100  
_0000  
LRC clock output = BCLK / LRCLK_RATE  
Integer (LSB = 1)  
Valid range: 8 to 2047  
Table 56 Digital Audio Interface Clock Control  
COMPANDING  
The WM8904 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides  
as shown in Table 57.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R24 (18h)  
ADC Companding Enable  
0 = disabled  
3
ADC_COMP  
0
Audio  
Interface 0  
1 = enabled  
ADC Companding Type  
0 = µ-law  
2
1
0
ADC_COMPMODE  
DAC_COMP  
0
0
0
1 = A-law  
DAC Companding Enable  
0 = disabled  
1 = enabled  
DAC Companding Type  
0 = µ-law  
DAC_COMPMODE  
1 = A-law  
Table 57 Companding Control  
Companding involves using a piecewise linear approximation of the following equations (as set out by  
ITU-T G.711 standard) for data compression:  
-law (where =255 for the U.S. and Japan):  
F(x) = ln( 1 + |x|) / ln( 1 + )  
A-law (where A=87.6 for Europe):  
F(x) = A|x| / ( 1 + lnA)  
-1 x 1  
x 1/A  
F(x) = ( 1 + lnA|x|) / (1 + lnA)  
1/A x 1  
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted  
for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSBs of  
data.  
Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This  
provides greater precision for low amplitude signals than for high amplitude signals, resulting in a  
greater usable dynamic range than 8 bit linear quantization. The companded signal is an 8-bit word  
comprising sign (1 bit), exponent (3 bits) and mantissa (4 bits).  
8-bit mode is selected whenever DAC_COMP=1 or ADC_COMP=1. The use of 8-bit data allows  
samples to be passed using as few as 8 BCLK cycles per LRCLK frame. When using DSP mode B,  
8-bit data words may be transferred consecutively every 8 BCLK cycles.  
PP, Rev 3.3, September 2012  
99  
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