WM8805
Production Data
CONTROL INTERFACE – 2-WIRE MODE
t STHO
tDSU
tSTHO
SDIN
t STSU
t STOP
SCLK
tSCY
t DH
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK cycle time
tSCY
2500
ns
%
SCLK duty cycle
40/60
60/40
400
SCLK frequency
kHz
ns
ns
ns
ns
ns
ns
ns
ns
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
tSTHO
tSTSU
tDSU
600
600
100
SDIN, SCLK Rise Time
SDIN, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
300
300
tSTOP
tDHO
tps
600
2
900
8
SCLK glitch suppression
Table 5 Control Interface Timing – 2-Wire Serial Control Mode
PD Rev 4.1 September 07
10
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
