Production Data
WM8805
CONTROL INTERFACE – 3-WIRE MODE
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK cycle time
tSCS
tSCY
60
80
ns
ns
%
SCLK duty cycle
40/60
20
60/40
SDIN to SCLK set-up time
SDIN hold time from SCLK rising edge
SDOUT propagation delay from SCLK rising edge
CSB pulse width high
tDSU
tDHO
tDL
ns
ns
ns
ns
ns
ns
20
5
8
tCSH
tCSS
tps
20
20
2
CSB rising/falling to SCLK rising
SCLK glitch suppression
Table 4 Control Interface Timing – 3-Wire Serial Control Mode
PD Rev 4.1 September 07
9
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
