WM8805
Production Data
DIGITAL AUDIO INTERFACE – SLAVE MODE
tBCH
tBCL
BCLK
LRCLK
DIN
tBCY
tLRSU
tDS
tLRH
tDD
tDH
DOUT
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
50
20
20
10
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK
rising edge
tLRSU
LRCLK hold time from
BCLK rising edge
tLRH
tDS
tDH
tDD
10
10
10
0
ns
ns
ns
ns
DIN set-up time to BCLK
rising edge
DIN hold time from BCLK
rising edge
DOUT propagation delay
from BCLK falling edge
10
Table 3 Digital Audio Data Timing – Slave Mode
PD Rev 4.1 September 07
8
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
