Production Data
WM8805
MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information – Slave Mode
MCLK System clock cycle time
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK Duty cycle
tMCLKY
tMCLKH
tMLCKL
27
11
ns
ns
ns
%
11
40:60
60:40
Table 1 Slave Mode MCLK Timing Requirements
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
tDL
LRCLK
tDDA
DOUT
DIN
tDST
Figure 2 Digital Audio Data Timing – Master Mode
Test Conditions
tDHT
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
LRCLK propagation delay from
BCLK falling edge
tDL
0
0
10
10
ns
ns
ns
ns
DOUT propagation delay from
BCLK falling edge
tDDA
tDST
tDHT
DIN setup time to BCLK rising
edge
10
10
DIN hold time from BCLK rising
edge
Table 2 Digital Audio Data Timing – Master Mode
PD Rev 4.1 September 07
7
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
