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WM8774
I2S MODE
In I2S mode, the MSB of DIN is sampled by the WM8774 on the second rising edge of BCLK
following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the
first falling edge of BCLK following an ADCLRC transition and may be sampled on the rising edge of
BCLK. ADCLRC and DACLRC are low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
BCLK
1 BCLK
1 BCLK
DIN/
DOUT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 11 I2S Mode TIming Diagram
DSP EARLY MODE
In DSP early mode, the MSB of DAC channel left data is sampled by the WM8774 on the second
rising edge on BCLK following a DACLRC rising edge (Figure 12).
1 BCLK
1 BCLK
1/fs
DACLRC
BCK
CHANNEL LEFT
CHANNEL RIGHT
NO VALID DATA
DIN
1
2
n
1
2
n
n-1
n-1
MSB
LSB
Word Length (IWL)
Figure 12 DSP Early Mode Timing Diagram – DAC Data Input
The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of
BCLK following a low to high ADCLRC transition and may be sampled on the rising edge of BCLK.
The right channel ADC data is contiguous with the left channel data (Figure 13)
1 BCLK
1 BCLK
1/fs
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n
1
2
n
n-1
n-1
MSB
LSB
Input Word Length (IWL)
Figure 13 DSP Early Mode Timing Diagram – ADC Data Output
PP Rev 1.0 June 2002
17
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
