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WM8777
Each ADC channel also has an individual mute control bit, which mutes the input to the ADC. The
ADCATC control bit allows the user to write the same attenuation value (LAG) to both left and right
volume control registers, saving on software writes. When setting the ADCATC function it is up to the
user to write a new gain value to take effect on both channels. When unsetting the ADCATC function
it is up to the user to write a new gain to both the left and right channel gains. The ATC function has
no effect when the ALC is enabled. The ADC volume and mute also applies to the bypass signal
path.
ADC OVERSAMPLING RATE SELECT
The signal processing for the WM8777 typically operates at an oversampling rate of 128fs for the
ADC (ADCOSR=0). The exception to this is for operation with a 128/192fs system clock, where the
oversampling rate is 64fs (ADCOSR=1). For the ADC operation at 96kHz in 256fs or 384fs mode it is
recommended that the user set the ADCOSR bit. This changes the ADC signal processing
oversample rate from 128fs to 64fs. For the ADC operation at 192KHz in 128fs or 192fs mode it is
recommended that the user set the ADCOSR bit. This changes the ADC signal processing
oversample rate from 64fs to 32fs.
The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled
using software control bit ADCHPD.
If the DAC and ADC are using the same MCLK source, and they are in compatible fs modes the
ADC and DAC will try to lock their respective clock generators together. This reduces the digital
noise on chip and helps the performance of the device. By default this is enabled, but can be
disabled by setting SYNC to 1.
REGISTER ADDRESS
(1Bh)
BIT
LABEL
DEFAULT
DESCRIPTION
ADC Highpass Filter Disable:
0 = Highpass Filter enabled
1 = Highpass Filter disabled
ADC oversample rate select
0 = 128x oversampling
ADC Interface Control
6
ADCHPD
0
7
8
ADCOSR
SYNC
0
0
1 = 64x oversampling
Sync ADC and DAC together.
0 = Enable SYNC function
1 = Disable Sync function
Table 69 ADC Functions Register
ADC INPUT MUX
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
(31h)
5:0
AIN[5:0]
00000
ADC input mixer control bits (see
Table 71)
ADC Mux and
Powerdown Control
Table 70 ADC Input Mux Register
Register bits AIN[5:0] control the left and right channel inputs into the stereo ADC. The default is
AIN1. However if the analogue input buffer is powered down, by setting AINPD, then all 12-channel
mux inputs are switched to buffered VMIDADC.
AIN[5:0]
ADC INPUT
00000
00001
00010
00011
00100
00101
……
MUTE
AIN1
AIN2
AIN1 + AIN2
AIN3
AIN3 + AIN1
…….
11111
AIN6 + AIN5 + AIN4 +AIN3 + AIN2 + AIN1
Table 71 ADC Input Mux Control
PP Rev 1.94 November 2004
67
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
