WM8777
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ADC CONTROL REGISTERS
ADC GAIN CONTROL
The ADC has an analogue input PGA and digital gain control for each stereo channel. Both
the analogue and digital gains are adjusted by the same register, LAG for the left and RAG
for the right. The analogue PGA has a range of +24dB to -21dB in 0.5dB steps. The digital
gain control allows further attenuation (after the ADC) from -21.5dB to -103dB in 0.5dB steps.
Table 68 shows how the register maps the analogue and digital gains.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
(2Eh)
7:0
LAG[7:0]
11001111
(0dB)
Attenuation control for left
channel ADC gain in 0.5dB
steps. See Table 68
Attenuation ADC Left
8
ZCLEN
0
Zero Cross enable for left
channel ADC
0 = Disable Zero Cross
1 = Enable Zero Cross
(2Fh)
7:0
8
RAG[7:0]
ZCREN
11001111
(0dB)
Attenuation control for right
channel ADC gain in 0.5dB
steps. See Table 68
Attenuation ADC Right
0
Zero Cross enable for right
channel ADC
0 = Disable Zero Cross
1 = Enable Zero Cross
Left Channel mute control
0 = Channel not muted
1 = Channel muted
(30h)
0
1
2
MUTEL
MUTER
ADCATC
0
0
0
Attenuation Control
Left Channel mute control
0 = Channel not muted
1 = Channel muted
Attenuator Control
0 = ADC use attenuations as
programmed.
1 = Right channel ADC use
corresponding left ADC
attenuations
3
TOADC
0
Time out clock enable/disable
0 = Time out clock enabled.
1 = Time out clock disabled.
Table 67 ADC Attenuation and Mute Registers
LAG/RAG[7:0]
ATTENUATION
LEVEL (AT
OUTPUT)
ANALOGUE PGA
DIGITAL
ATTENUATION
00(hex)
01(hex)
:
-∞ dB (mute)
-21dB
-21dB
:
Digital mute
-103dB
-82dB
:
:
-21.5dB
-21dB
:
A4(hex)
A5(hex)
:
-21dB
-21dB
:
-0.5dB
0dB
:
CF(hex)
:
0dB
0dB
0dB
:
:
:
FE(hex)
FF(hex)
+23.5dB
+24dB
+23.5dB
+24dB
0dB
0dB
Table 68 Analogue and Digital Gain Mapping for ADC
In addition a zero cross detect circuit is provided for the output PGA volume under the control of bit 7
(ZCEN) in the each attenuation register. When ZCEN is set the attenuation values are only updated
when the input signal to the gain stage is close to the analogue ground level. This minimises audible
clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which will
generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of
12.288MHz). The timeout clock may be disabled by setting TOADC.
PP Rev 1.94 November 2004
66
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
