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WM8777SEFT 参数 Datasheet PDF下载

WM8777SEFT图片预览
型号: WM8777SEFT
PDF下载: 下载PDF文件 查看货源
内容描述: 24位192KHZ AV接收机芯片 [24 BIT 192KHZ AV RECEIVER ON A CHIP]
分类和应用: 接收机
文件页数/大小: 102 页 / 1257 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8777  
Product Preview  
L/RDAX[7:0]  
ATTENUATION LEVEL  
00(hex)  
-dB (mute)  
01(hex)  
-127.5dB  
:
:
:
:
:
:
FE(hex)  
FF(hex)  
-0.5dB  
0dB  
Table 63 Digital Volume Control Attenuation Levels  
The Digital volume control also incorporates a zero cross detect circuit which detects a transition  
through the zero point before updating the digital volume control with the new volume. This is  
enabled by control bit DZCEN.  
REGISTER ADDRESS  
(15h)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
0
DZCEN  
0
DAC Digital Volume Zero Cross  
Enable:  
DAC Attenuation Control  
0 = Zero Cross detect disabled  
1 = Zero Cross detect enabled  
Table 64 Digital Zero Cross Register  
DAC OUTPUT PHASE  
The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted  
REGISTER ADDRESS  
(14h)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
7:0  
PHASE  
[7:0]  
00000000  
Controls phase of DAC outputs  
DAC Output Phase  
PHASE[0] = 1 inverts phase of  
DAC1L output  
PHASE[1] = 1 inverts phase of  
DAC1R output  
PHASE[2] = 1 inverts phase of  
DAC2L output  
PHASE[3] = 1 inverts phase of  
DAC2R output  
PHASE[4] = 1 inverts phase of  
DAC3L output  
PHASE[5] = 1 inverts phase of  
DAC3R output  
PHASE[6] = 1 inverts phase of  
DAC4L output  
PHASE[7] = 1 inverts phase of  
DAC4R output  
Table 65 DAC Output Phase Register  
PP Rev 1.94 November 2004  
64  
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