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WM8777SEFT 参数 Datasheet PDF下载

WM8777SEFT图片预览
型号: WM8777SEFT
PDF下载: 下载PDF文件 查看货源
内容描述: 24位192KHZ AV接收机芯片 [24 BIT 192KHZ AV RECEIVER ON A CHIP]
分类和应用: 接收机
文件页数/大小: 102 页 / 1257 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8777  
MAXIMUM GAIN (ALC ONLY) AND MAXIMUM ATTENUATION  
To prevent low level signals being amplified too much by the ALC, the MAXGAIN register sets the  
upper limit for the gain. This prevents low level noise being over-amplified. The MAXGAIN register  
has no effect on the limiter operation.  
The MAXATTEN register has different operation for the limiter and for the ALC. For the limiter it  
defines the maximum attenuation below the static (user programmed) gain. For the ALC, it defines  
the lower limit for the gain.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
(1Dh)  
6:4  
MAXGAIN[2:0]  
111  
(+24dB)  
Set maximum gain for the PGA (ALC  
only)  
ALC Control 1  
111 = +24dB  
110 = +20dB  
…..(-4dB steps)  
010 = +4dB  
001 = 0dB  
000 = 0dB  
(21h)  
3:0  
MAXATTEN  
[3:0]  
0110  
Maximum attenuation of PGA  
Limiter Control  
Limiter  
(attenuation  
below static)  
ALC (lower PGA  
gain limit)  
1010 or lower  
= -1dB  
0000 = -3dB  
0001 = -4dB  
0010 = -5dB  
…. (-1dB steps)  
1001 = -12dB  
1011 = -5dB  
….. (-4dB steps)  
1110 = -17dB  
1111 = -21dB  
Table 77 ALC MAXGAIN and MAXATTEN Registers  
HOLD TIME (ALC ONLY)  
The ALC also has a hold time, which is the time delay between the peak level detected being below  
target and the PGA gain beginning to ramp up. It can be programmed in power-of-two (2n) steps, e.g.  
2.67ms, 5.33ms, 10.67ms etc. up to 43.7ms. Alternatively, the hold time can also be set to zero. The  
hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the  
signal level is above target.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
(1Eh)  
3:0  
HLD[3:0]  
0000  
ALC hold time before gain is  
increased.  
ALC Control 2  
0000 = 0ms  
0001 = 2.67ms  
0010 = 5.33ms  
… (time doubles with every step)  
1111 = 43.691s  
Table 78 ALC Hold Time Register  
OVERLOAD DETECTOR (ALC ONLY)  
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes an  
overload detector. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is  
ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below  
87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.  
(Note: If ATK = 0000, then the overload detector makes no difference to the operation of the ALC. It  
is designed to prevent clipping when long attack times are used).  
PP Rev 1.94 November 2004  
71  
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