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WM8777SEFT 参数 Datasheet PDF下载

WM8777SEFT图片预览
型号: WM8777SEFT
PDF下载: 下载PDF文件 查看货源
内容描述: 24位192KHZ AV接收机芯片 [24 BIT 192KHZ AV RECEIVER ON A CHIP]
分类和应用: 接收机
文件页数/大小: 102 页 / 1257 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Product Preview  
WM8777  
DAC DIGITAL VOLUME CONTROL  
The DAC volume may also be adjusted in the digital domain using independent digital attenuation  
control registers  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
(0Bh)  
7:0  
LDA1[7:0]  
11111111  
(0dB)  
Digital Attenuation control for DAC1 Left Channel (LSUMOP) in  
0.5dB steps. See Table 63  
Digital  
Attenuation  
DACL1  
8
UPDATE  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store LDA1 in intermediate latch (no change to output)  
1 = Store LDA1 and update attenuation on all channels  
(0Ch)  
7:0  
8
RDA1[6:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation control for DAC1 Right Channel (RSUMOP) in  
0.5dB steps. See Table 63  
Digital  
Attenuation  
DACR1  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store RDA1 in intermediate latch (no change to output)  
1 = Store RDA1 and update attenuation on all channels.  
(0Dh)  
7:0  
8
LDA2[7:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation control for DAC2 Left Channel (CNTSOP) in  
0.5dB steps. See Table 63  
Digital  
Attenuation  
DACL2  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store LDA2 in intermediate latch (no change to output)  
1 = Store LDA2 and update attenuation on all channels.  
(0Eh)  
7:0  
8
RDA2[7:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation control for DAC2 Right Channel (LFESOP) in  
0.5dB steps. See Table 63  
Digital  
Attenuation  
DACR2  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store RDA2 in intermediate latch (no change to output)  
1 = Store RDA2 and update attenuation on all channels.  
(0Fh)  
7:0  
8
LDA3[7:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation control for DAC3 Left Channel (LSURSOP) in  
0.5dB steps. See Table 63  
Digital  
Attenuation  
DACL3  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store LDA3 in intermediate latch (no change to output)  
1 = Store LDA3 and update attenuation on all channels.  
(10h)  
7:0  
8
RDA3[7:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation control for DAC3 Right Channel (RSURSOP) in  
0.5dB steps. See Table 63  
Digital  
Attenuation  
DACR3  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store RDA3 in intermediate latch (no change to output)  
1 = Store RDA3 and update attenuation on all channels.  
(11h)  
7:0  
8
LDA4[7:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation control for DAC4 Left Channel (LAUXSOP) in  
0.5dB steps. See Table 63  
Digital  
Attenuation  
DACL4  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store LDA4 in intermediate latch (no change to output)  
1 = Store LDA4 and update attenuation on all channels.  
(12h)  
7:0  
8
RDA4[7:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation control for DAC4 Right Channel (RAUXSOP) in  
0.5dB steps. See Table 63  
Digital  
Attenuation  
DACR4  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store RDA4 in intermediate latch (no change to output)  
1 = Store RDA4 and update attenuation on all channels.  
(13h)  
7:0  
8
MASTDA[7:0]  
UPDATE  
11111111  
(0dB)  
Digital Attenuation control for all DAC channels in 0.5dB steps. See  
Table 63  
Digital  
Attenuation  
Not latched  
Controls simultaneous update of all Attenuation Latches  
0 = Store gain in intermediate latch (no change to output)  
1 = Store gain and update attenuation on all channels.  
Master  
(all channels)  
Table 62 Digital Attenuation Registers  
PP Rev 1.94 November 2004  
63  
w
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