WM8777
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
(0Ah)
6:0
MASTA[6:0]
1101011
(0dB)
0
Analogue Attenuation control for all DAC gains in 1dB steps. See
Table 60.
Analogue
Attenuation
7
8
MZCEN
Master zero cross detect enable
Master
0 = zero cross disabled
(all channels)
1 = zero cross enabled
UPDATE
Not latched
Controls simultaneous update of all Analogue Attenuation Latches
0 = Store gains in intermediate latch (no change to output)
1 = Store gains and update attenuation on all channels.
Table 59 Analogue Attenuation Registers
Each analogue output channel volume can be controlled digitally in an analogue volume stage after
the DAC. Attenuation is 0dB by default but can be set between +20dB and –100dB in 1dB steps
using the 7 Attenuation control words. All attenuation registers are double latched allowing new
values to be pre-latched to several channels before being updated synchronously. Setting the
UPDATE bit on any attenuation write will cause all pre-latched values to be immediately applied to
the DAC channels. A master attenuation register is also included, allowing all volume levels to be set
to the same value in a single write.
Note: The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-
latch but not applied to the relevant ouptut. If UPDATE=1, all pre-latched values will be applied from
the next input sample. Writing to MASTA[6:0] overwrites any values previously sent to FRONTL[6:0],
CNTR[6:0], SURL[6:0], AUXL[6:0], FRONTR[6:0], LFE[6:0], SURR[6:0], AUXR[6:0].
Register bits FRONTL and FRONTR control the left and right channel attenuation of the Front
channels. Register bits CNTR and LFE control the left and right channel attenuation of CNTR and
LFE respectively. Register bits SURL and SURR control the left and right channel attenuation of
surround channels. Register bits AUXL and AUXR control the left and right channel attenuation of the
auxiliary channel. Register bits MASTA can be used to control attenuation of all channels.
Table 60 shows how the attenuation levels are selected from the 7-bit words.
L/RAx[6:0]
00(hex)
:
ATTENUATION LEVEL
-∞dB (mute)
:
06(hex)
07(hex)
:
-∞dB (mute)
-100dB
:
6B(hex)
7D(hex)
7E(hex)
7F(hex)
0dB (default)
+18dB
+19dB
+20dB
Table 60 Analogue Volume Control Attenuation Levels
In addition a zero cross detect circuit is provided for each analogue output volume under the control
of bit 7 (xZCEN) in each Analogue attenuation register. When ZCEN is set the attenuation values are
only updated when the input signal to the gain stage is close to the analogue ground level. This
minimises audible clicks and ‘zipper’ noise as the gain values change. A timeout clock is also
provided which will generate an update after a minimum of 131072 master clocks ( ~10.5ms with a
master clock of 12.288MHz). The timeout clock may be disabled by setting TOCDAC.
REGISTER ADDRESS
(15h)
BIT
LABEL
DEFAULT
DESCRIPTION
4
TOCDAC
0
DAC Analogue Zero cross detect
timeout disable
Timeout Clock Disable
0 = Timeout enabled
1 = Timeout disabled
Table 61 Timeout Clock Disable Register
PP Rev 1.94 November 2004
62
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
