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WM8777
SAMPLING
SYSTEM CLOCK FREQUENCY (MHZ)
RATE
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
(PDATAIPLRC/
PDATAOPLRC)
PAIFTX_RATE/
PAIFRX_RATE/
SAIFRATE
=000
PAIFTX_RATE/
PAIFRX_RATE/
SAIFRATE
=001
PAIFTX_RATE/
PAIFRX_RATE/
SAIFRATE
=010
PAIFTX_RATE/
PAIFRX_RATE/
SAIFRATE
=011
PAIFTX_RATE/
PAIFRX_RATE/
SAIFRATE
=100
PAIFTX_RATE/
PAIFRX_RATE/
SAIFRATE
=101
PAIFTX_RATE/
PAIFRX_RATE/
SAIFRATE
=110
32kHz
44.1kHz
48kHz
4.096
5.6448
6.144
6.144
8.467
8.192
11.2896
12.288
12.288
16.9340
18.432
16.384
22.5792
24.576
33.8688
36.864
Unavailable
Unavailable
Unavailable
Unavailable
9.216
24.576
36.864
96kHz
12.288
24.576
18.432
36.864
24.576
36.864
Unavailable
Unavailable
Unavailable
Unavailable
192kHz
Unavailable
Unavailable
Table 21 Master Mode ADC/PDATAIPLRC Frequency Selection
PBCLK is also generated by the WM8777. The frequency of PBCLK depends on the mode of
operation. In 128/192fs modes (PAIFTX_RATE/PAIFRX_RATE=000 or 001) PBCLK = MCLK/2. In
256/384/512/768/1152fs modes (PAIFTX_RATE/PAIFRX_RATE=010 or 011 or 100 or 101 or 110)
PBCLK = MCLK/4. However if DSP mode is selected as the audio interface mode then
PBCLK=MCLK. This is to ensure that there are sufficient PBCLKs to clock in all eight channels. Note
that DSP mode cannot be used in 128fs mode for word lengths greater than 16-bits or in 192fs mode
for word lengths greater than 24 bits.
Figure 15 Digital Audio Data Timing – Master Mode
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
PDATAOPLRC/PDATAIPL
RC propagation delay from
PBCLK falling edge
tDL
0
10
ns
PDATAOP propagation
delay from PBCLK falling
edge
tDDA
0
10
ns
PDATAIP1/2/3/4 setup time
to PBCLK rising edge
tDST
tDHT
10
10
ns
ns
PDATAIP1/2/3/4 hold time
from PBCLK rising edge
Table 22 Digital Audio Data Timing – Master Mode
PP Rev 1.94 November 2004
33
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
