Product Preview
WM8777
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
PBCLK cycle time
tBCY
tBCH
tBCL
50
20
20
10
ns
ns
ns
ns
PBCLK pulse width high
PBCLK pulse width low
PDATAIPLRC/PDATAOPL
RC set-up time to PBCLK
rising edge
tLRSU
PDATAIPLRC/PDATAOPL
RC hold time from PBCLK
rising edge
tLRH
10
ns
PDATAIP1/2/3/4 set-up
time to PBCLK rising edge
tDS
tDH
tDD
10
10
0
ns
ns
ns
PDATAIP1/2/3/4 hold time
from PBCLK rising edge
PDATAOP propagation
delay from PBCLK falling
edge
10
Table 17 Digital Audio Data Timing – Slave Mode
Note: PDATAOPLRC and PDATAIPLRC should be synchronous with MCLK, although the WM8777 interface is tolerant of
phase variations or jitter on these signals.
The DACs support system clock to sampling clock ratios of 256fs to 1152fs when the DAC signal
processing of the WM8777 is programmed to operate at 128 times oversampling rate (DACOSR=0).
The DACs support ratios of 128fs and 192fs when the WM8777 is programmed to operate at 64
times oversampling rate (DACOSR=1).
The ADC supports system clock to sampling clock ratios of 128fs to 1152fs. The signal processing
for the WM8777 ADC typically operates at an oversampling rate of 128fs. For ADC operation at
96kHz in 256fs or 384fs mode it is recommended that the user set the ADCOSR bit. This changes
the ADC signal processing oversample rate from 128fs to 64fs. For ADC operation at 192kHz in
128fs or 192fs mode it is recommended that the user set the ADCOSR bit. This changes the ADC
signal processing oversample rate from 64fs to 32fs.
Table 18 shows the typical system clock frequencies for ADC operation at both 128 times
oversampling rate (ADCOSR=0) and 64 times oversampling rate (ADCOSR=1), and DAC operation
at 128 times oversampling rate (DACOSR=0). Table 19 shows typical system clock frequencies for
ADC operation at 32/64 times oversampling rate (ADCOSR=1), and DAC operation at 64 times
oversampling rate (DACOSR =1).
SAMPLING
RATE
System Clock Frequency (MHz)
256fs
384fs
512fs
768fs
1152fs
(PDATAIPLRC/
PDATAOPLRC)
32kHz
44.1kHz
48kHz
8.192
11.2896
12.288
24.576
12.288
16.9340
18.432
36.864
16.384
22.5792
24.576
24.576
33.8688
36.864
36.864
Unavailable
Unavailable
96kHz
Unavailable Unavailable Unavailable
Table 18 ADC and DAC system clock frequencies versus sampling rate. (ADC operation at
either 128 times oversampling rate (ADCOSR=0) or 64 times oversampling rate (ADCOSR=1),
DAC operation at 128 times oversampling rate, DACOSR=0)
PP Rev 1.94 November 2004
31
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
