WM8777
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AUDIO SAMPLING RATES AND AUDIO INTERFACES
DIGITAL AUDIO INTERFACES
The WM8777 has two audio interfaces – a primary audio interface and a secondary audio interface.
The primary audio interface has four data inputs (PDATAIP1/2/3/4), one data output (PDATAOP),
and is controlled by PBCLK, PDATAOPLRC and PDATAIPLRC clock pins. The secondary audio
interface has one input (SDATAIP), one output (SDATAOP) and is controlled by SPBCLK and SLRC
clock pins.
Both audio interfaces operate in either Slave or Master mode, selectable using the PAIFRX_MS and
SMS control bits. In both Master and Slave modes PDATAIP1/2/3/4 and SDATAIP are always inputs
to the WM8777 and PDATAOP and SDATAOP are always outputs. The default is Slave mode.
SLAVE MODE
In Slave mode (PAIFRX_MS/SMS=0) PDATAOPLRC, PDATAIPLRC, SLRC, PBCLK and SPBCLK
are inputs to the WM8777. PDATAIP1/2/3/4, PDATAOPLRC and PDATAIPLRC are sampled by the
WM8777 on the rising edge of PBCLK. SDATAIP and SLRC are sampled by the WM8777 on the
rising edge of SBCLK. Data output PDATAOP changes on the falling edge of PBCLK and data output
on SDATAOP changes on the falling edge of SBCLK. By setting control bit PAIFRX_BCP the polarity
of PBCLK may be reversed so that PDATAIP1/2/3/4, PDATAOPLRC and PDATAIPLRC are sampled
on the falling edge of PBCLK and PDATAOP changes on the rising edge of PBCLK. Similarly the
polarity of SBCLK can be reversed using control bit SBCP.
Figure 12 Digital Audio Interface – Slave Mode
Figure 13 Digital Audio Data Timing – Slave Mode
PP Rev 1.94 November 2004
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
