WM8777
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RIGHT JUSTIFIED MODE
In right justified mode, the LSB of the input data (PDATAIP/SDATAIP) is sampled by the WM8777 on
the rising edge of PBCLK/SPBCLK preceding a LRCLK transition. The LSB of the output data
(PDATAOP/SDATOP) changes on the falling edge of PBCLK preceding a LRCLK transition, and may
be sampled on the nect rising edge of PBCLK. LRCLKs are high during the left samples and low
during the right samples (Figure 17).
Figure 17 Right Justified Mode Timing Diagram
I2S MODE
In I2S mode, the MSB of the input data is sampled by the WM8777 on the second rising edge of
PBCLK/SPBCLK following a LRCLK transition. The MSB of the output data changes on the first
falling edge of PBCLK following an LRCLK transition, and may be sampled on the next rising edge of
PBCLK. LRCKs are low during the left samples and high during the right samples.
Figure 18 I2S Mode Timing Diagram
DSP EARLY MODE
In DSP early mode, the MSB of DAC channel 1 left data is sampled by the WM8777 on the second
rising edge on PBCLK following a PDATAIPLRC rising edge. DAC channel 1 right and DAC channels
2, 3 and 4 data follow DAC channel 1 left data (Figure 19).
Figure 19 DSP Early Mode Timing Diagram – DAC Data Input
PP Rev 1.94 November 2004
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
