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WM8777
AUDIO INTERFACE FORMATS
Audio data is applied to the WM8777 via the Primary and Secondary Audio Interface. Five popular
interface formats are supported:
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Left Justified mode
Right Justified mode
I2S mode
DSP Early mode
DSP Late mode
All five formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the
exception of 32 bit right justified mode, which is not supported.
Audio Data for each stereo channel is time multiplexed with the interface’s Left-Right-Clock
(PDATAOPLRC/PDATAIPLRC), indicating whether the left or right channel is present. The
PDATAOPLRC/PDATAIPLRC is also used as a timing reference to indicate the beginning or end of
the data words.
In left justified, right justified and I²S modes, the minimum number of PBCLKs per LRCLK period is 2
times the selected word length. LRCLK must be high for a minimum of word length PBCLKs and low
for a minimum of word length PBCLKs. Any mark to space ratio on LRCLK is acceptable provided
the above requirements are met. The Primary Audio interface has Left-Right-Clocks PDATAOPLRC
and PDATAIPLRC, and Bit-Clock PBCLK. The Secondary Audio Interface has Left-Right-Clock
SLRC, and Bit-Clock SPBCLK.
In DSP early or DSP late mode, all 8 DAC channels are time multiplexed onto PDATAIP1.
PDATAIPLRC is used as a frame sync signal to identify the MSB of the first word. The minimum
number of PBCLKs per PDATAIPLRC period is 8 times the selected word length. Any mark to space
ratio is acceptable on PDATAIPLRC provided the rising edge is correctly positioned. The ADC data
may also be output in DSP early or late modes, with PDATAOPLRC used as a frame sync to identify
the MSB of the first word. The minimum number of PBCLKs per PDATAOPLRC period is 2 times the
selected word length. The Secondary Audio Interface also supports DSP modes with SLRC used as
a frame sync and data input on SDATAIP, and data output on SDATAOP. The minimum number of
SPBCLKs per SLRC period is 2 times the selected word length.
LEFT JUSTIFIED MODE
In left justified mode, the MSB of the input data (PDATAIP/SDATAIP) is sampled by the WM8777 on
the first rising edge of PBCLK/SPBCLK following a LRCLK transition. The MSB of the output data
(PDATAOP/SDATAOP) changes on the same falling edge of PBCLK as SLRC, and may be sampled
on the next rising edge of PBCLK. LRCLKs are high during the left samples and low during the right
samples.
Figure 16 Left Justified Mode Timing Diagram
PP Rev 1.94 November 2004
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
