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WM8777
MASTER CLOCK
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. The external master system clock can be applied directly through the MCLK input pin
with no software configuration necessary. In a system where there are a number of possible sources
for the reference clock it is recommended that the clock source with the lowest jitter be used to
optimise the performance of the ADC and DAC.
MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKP
Figure 11 Master Clock Timing Requirements
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK Duty cycle
tMCLKH
tMCLKL
tMCLKP
11
11
ns
ns
ns
28
40:60
60:40
Table 16 Master Clock Timing Requirements
The master clock for WM8777 supports DAC and ADC audio sampling rates from 128fs to 1152fs,
where fs is the audio sampling frequency (PDATAIPLRC or PDATAOPLRC) typically 32kHz,
44.1kHz, 48kHz, 96kHz, or 192KHz. The master clock is used to operate the digital filters and the
noise shaping circuits.
The WM8777 has a master clock detection circuit that automatically determines the relationship
between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If there is
a greater than 32 clocks error the interface sets itself to the highest rate available, 1152fs. The
master clock must be synchronised with PDATAOPLRC/PDATAIPLRC, although the WM8777 is
tolerant of phase variations or jitter on this clock.
PP Rev 1.94 November 2004
29
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
