WM8777
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SAMPLING
RATE
System Clock Frequency (MHz)
128fs
192fs
(PDATAIPLRC/
PDATAOPLRC)
96kHz
12.288
24.576
18.432
36.864
192kHz
Table 19 ADC and DAC system clock frequencies versus sampling rate. (ADC operation at
32/64 times oversampling rate (ADCOSR=1), DAC operation at 64 times oversampling rate
(DACOSR=1)
MASTER MODE
In Master mode PBCLK, PDATAIPLRC, PDATAOPLRC, SLRC and SPBCLK are generated by the
WM8777.
Figure 14 Audio Interface - Master Mode
The frequencies of PDATAOPLRC, PDATAIPLRC and SLRC are set by setting the required ratio of
MCLK to PDATAIPLRC, PDATAOPLRC and SLRC using the PAIFRX_RATE, PAIFTX_RATE and
SAIFRATE control bits respectively, see Table 20.
PAIFTX_RATE[2:0]/
PAIFRX_RATE[2:0]
MCLK :
PDATAOPLRC/PDATAIPLR
C/SLRC RATIO
000
001
010
011
100
101
110
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
Table 20 Master Mode MCLK:LRCLK Ratio Select
Table 21 shows the settings for PAIFTX_RATE, PAIFRX_RATE and SAIFRATE for common sample
rates and MCLK frequencies.
PP Rev 1.94 November 2004
32
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
