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WM8777
The MSB of the left channel ADC data is output on PDATAOP and changes on the first falling edge
of PBCLK following a low to high PDATAOPLRC transition and may be sampled on the rising edge of
PBCLK. The right channel ADC data is contiguous with the left channel data (Figure 20).
Figure 20 DSP Early Mode Timing Diagram – ADC Data Output
DSP LATE MODE
In DSP late mode, the MSB of DAC channel 1 left data is sampled by the WM8777 on the first
PBCLK rising edge following a PDATAIPLRC rising edge. DAC channel 1 right and DAC channels 2,
3 and 4 data follow DAC channel 1 left data (Figure 21).
Figure 21 DSP Late Mode Timing Diagram – DAC Data Input
The MSB of the left channel ADC data is output on PDATAOP and changes on the same falling edge
of PBCLK as the low to high PDATAOPLRC transition and may be sampled on the rising edge of
PBCLK. The right channel ADC data is contiguous with the left channel data (Figure 22).
Figure 22 DSP Late Mode Timing Diagram – ADC Data Output
In both early and late DSP modes, DACL1 is always sent first, followed immediately by DACR1 and
the data words for the other 6 channels. No PBCLK edges are allowed between the data words. The
word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right, DAC4 left, DAC4
right. For DSP modes the Secondary Audio Interface exhibits similar timing to the ADC where data is
input on SDATAIP, and output on SDATAOP.
PP Rev 1.94 November 2004
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
