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WM8773
In Master mode BCLK and ADCLRC are generated by the WM8773. The frequency of ADCLRC is
determined by setting the required ratio of MCLK to ADCLRC using the ADCRATE control bits (Table
6).
ADCRATE[2:0]
MCLK:ADCLRC RATIO
010
011
100
101
256fs
384fs
512fs
768fs
Table 6 Master Mode MCLK:ADCLRC ratio select
Table 7 shows the settings for ADCRATE for common sample rates and MCLK frequencies.
SAMPLING
RATE
System Clock Frequency (MHz)
256fs
384fs
512fs
768fs
ADCLRC
ADCRATE
=010
ADCRATE
=011
ADCRATE
=100
ADCRATE
=101
32kHz
44.1kHz
48kHz
8.192
11.2896
12.288
24.576
12.288
16.9340
18.432
36.864
16.384
22.5792
24.576
24.576
33.8688
36.864
96kHz
Unavailable Unavailable
Table 7 Master Mode ADC frequency selection
BCLK is also generated by the WM8773. The frequency of BCLK depends on the mode of operation.
In 256/384/512fs modes (ADCRATE=010 or 011, 100 or 101) BCLK = MCLK/4. However if DSP
mode is selected as the audio interface mode then BCLK=MCLK.
POWERDOWN MODES
The WM8773 has powerdown control bits allowing specific parts of the WM8773 to be powered off
when not being used. The 8-channel input source selector and input buffer may be powered down
using control bit AINPD. When AINPD is set all inputs to the source selector (AIN1l/R to AIN8L/R)
are switched to a buffered VMIDADC. Control bit ADCPD powers off the ADC and also the ADC input
PGAs. Setting AINPD and ADCPD will powerdown everything except the references VMIDADC and
ADCREF. These may be powered down by setting PDWN. Setting PDWN will override all other
powerdown control bits. It is recommended that the 8-channel input mux and buffer and ADC are
powered down before setting PDWN. The default is for all powerdown bits to be set except PDWN.
The Powerdown control bits allow parts of the device to be powered down when not in use.
DIGITAL AUDIO INTERFACE
MASTER AND SLAVE MODES
The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In
both Master and Slave modes, ADCDAT is always an output. The default is Slave mode.
In Slave mode (MS=0) ADCLRC and BCLK are inputs to the WM8773 (Figure 7). ADCLRC is
sampled by the WM8773 on the rising edge of BCLK. ADC data is output on DOUT and changes on
the falling edge of BCLK. By setting control bit BCLKINV the polarity of BCLK may be reversed so
that ADCLRC is sampled on the falling edge of BCLK and DOUT changes on the rising edge of
BCLK.
PP Rev 1.0 June 2002
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
