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WM8773
BCLK
(Output)
tDL
ADCLRC
tDDA
DOUT
Figure 3 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCLRC propagation delay
from BCLK falling edge
tDL
0
0
10
10
ns
ns
DOUT propagation delay
from BCLK falling edge
tDDA
Table 2 Digital Audio Data Timing – Master Mode
DIGITAL AUDIO INTERFACE – SLAVE MODE
BCLK
DSP
WM8773
CODEC
ENCODER/
DECODER
ADCLRC
DOUT
Figure 4 Audio Interface – Slave Mode
PP Rev 1.0 June 2002
9
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