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WM8773
DSP LATE MODE
The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of
BCLK as the low to high ADCLRC transition and may be sampled on the rising edge of BCLK. The
right channel ADC data is contiguous with the left channel data (Figure 13).
1/fs
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
1
2
n
1
2
n
1
DOUT
n-1
n-1
MSB
LSB
Word Length (WL)
Figure 13 DSP Late Mode Timing Diagram – ADC Data Output
CONTROL INTERFACE OPERATION
The WM8773 is controlled using a 3-wire SPI compatible serial configuration.
The control interface is 5V tolerant, meaning that the control interface input signals CE, CL and DI
may have an input high level of 5V while DVDD is 3V. Input thresholds are determined by DVDD.
RESETB is also 5V tolerant.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
DI is used for the program data, CL is used to clock in the program data and CE is used to latch the
program data. DI is sampled on the rising edge of CL. The 3-wire interface protocol is shown in
Figure 14.
CE
CL
DI
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 14 3-wire SPI compatible Interface
Note:
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
3. CE is edge sensitive – the data is latched on the rising edge of CE.
PP Rev 1.0 June 2002
17
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
