WM8773
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tBCH
tBCL
BCLK
tBCY
ADCLRC
DOUT
tDD
Figure 5 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
tDD
50
20
20
0
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
DOUT propagation delay
from BCLK falling edge
10
Table 3 Digital Audio Data Timing – Slave Mode
Note:
1. ADCLRC should be synchronous with MCLK, although the WM8773 interface is tolerant of phase variations or jitter on
these signals.
PP Rev 1.0 June 2002
10
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
