Product Preview
WM8773
MPU INTERFACE TIMING
tRCSU
tRCHO
RESETB
CE
tCSL
tCSH
tSCY
tCSS
tSCS
tSCH
tSCL
CL
DI
LSB
tDSU
tDHO
Figure 6 SPI compatible Control Interface Input Timing
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated
PARAMETER
CE to RESETB hold time
SYMBOL
tRCSU
tRCHO
tSCS
MIN
20
20
60
80
30
30
20
20
20
20
20
TYP
MAX
UNIT
ns
RESETB to CL setup time
CL rising edge to CE rising edge
CL pulse cycle time
CL pulse width low
ns
ns
tSCY
ns
tSCL
ns
CL pulse width high
DI to CL set-up time
CL to DI hold time
tSCH
ns
tDSU
ns
tDHO
ns
CE pulse width low
tCSL
ns
CE pulse width high
CE rising to CL rising
tCSH
ns
tCSS
ns
Table 4 3-wire SPI compatible Control Interface Input Timing Information
PP Rev 1.0 June 2002
11
ꢀꢀ
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
