WM8773
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DEVICE DESCRIPTION
INTRODUCTION
WM8773 is a complete stereo audio ADC with 8-channel multiplexed input.
The input multiplexor to the ADC is configured to allow large signal levels to be input to the ADC,
using external resistors to reduce the amplitude of larger signals to within the normal operating range
of the ADC. The ADC input PGA also allows input signals to be gained up to +19dB and attenuated
down to -12dB. This allows the user maximum flexibility in the use of the ADC.
Analogue record monitor outputs are also available, to allow stereo analogue signals from any of the
8 stereo inputs to be sent to sent to one of the two stereo outputs. This allows the user to monitor
the signal that is being digitised either prior to the input programmable gain amplifier (PGA) or after
gain has been applied. It is intended that the RECL/R outputs are only used to drive a high
impedance buffer.
The Audio Interface may be configured to operate in either master or slave mode. In Slave mode
ADCLRC and BCLK are both inputs. In Master mode ADCLRC and BCLK are all outputs.
Control of internal functionality of the device is by 3-wire serial control interface. The control interface
may be asynchronous to the audio data interface as control data will be re-synchronised to the audio
processing internally. CE, CL, DI and RESETB are 5V tolerant with TTL input thresholds, allowing
the WM8773 to used with DVDD = 3.3V and be controlled by a controller with 5V output.
Operation using system clock of 256fs, 384fs, 512fs or 768fs is provided. In Slave mode selection
between clock rates is automatically controlled. In master mode the master clock to sample rate ratio
is set by control bit ADCRATE. Sample rates (fs) from less than 8ks/s up to 96ks/s are allowed,
provided the appropriate system clock is input.
The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP
serial port interface.
AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. The external master system clock can be applied directly through the MCLK input pin
with no software configuration necessary. In a system where there are a number of possible sources
for the reference clock it is recommended that the clock source with the lowest jitter be used to
optimise the performance of the ADC.
The master clock for WM8773 supports ADC audio sampling rates from 256fs to 768fs, where fs is
the audio sampling frequency (ADCLRC) typically 32kHz, 44.1kHz, 48kHz or 96kHz. The master
clock is used to operate the digital filters and the noise shaping circuits.
In Slave mode the WM8773 has a master detection circuit that automatically determines the
relationship between the master clock frequency and the sampling rate (to within +/- 32 system
clocks). If there is a greater than 32 clocks error the interface is disabled and maintains the output
level at the last sample. The master clock must be synchronised with ADCLRC, although the
WM8773 is tolerant of phase variations or jitter on this clock. Table 5 shows the typical master clock
frequency inputs for the WM8773.
The signal processing for the WM8773 typically operates at an oversampling rate of 128fs for the
ADC. For ADC operation at 96kHz, it is recommended that the user set the ADCOSR bit. This
changes the ADC signal processing oversample rate to 64fs.
SAMPLING
RATE
System Clock Frequency (MHz)
256fs
384fs
512fs
768fs
(ADCLRC)
32kHz
44.1kHz
48kHz
8.192
11.2896
12.288
12.288
16.9340
18.432
16.384
22.5792
24.576
24.576
33.8688
36.864
Table 5 System Clock Frequencies Versus Sampling Rate
PP Rev 1.0 June 2002
12
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
