WM8773
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BCLK
ADCLRC
DOUT
DSP
ENCODER/
DECODER
WM8773
CODEC
Figure 7 Slave Mode
In Master mode (MS=1) ADCLRC and BCLK are outputs from the WM8773 (Figure 8). ADCLRC and
BITCLK are generated by the WM8773. ADCDAT is output on DOUT and changes on the falling
edge of BCLK. By setting control bit BCLKINV the polarity of BCLK may be reversed so that DOUT
changes on the rising edge of BCLK.
BCLK
DSP/
WM8773
ADC
ENCODER/
ADCLRC
DOUT
DECODER
Figure 8 Master Mode
AUDIO INTERFACE FORMATS
Audio data is output from the ADC filters, via the Digital Audio Interface. 5 popular interface formats
are supported:
•
•
•
•
•
Left Justified mode
Right Justified mode
I2S mode
DSP Early mode
DSP Late mode
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the
exception of 32 bit right justified mode, which is not supported.
In left justified, right justified and I2S modes, the digital audio interface outputs ADC data on DOUT.
Audio Data for each stereo channel is time multiplexed with ADCLRC indicating whether the left or
right channel is present. ADCLRC is also used as a timing reference to indicate the beginning or end
of the data words.
In left justified, right justified and I2S modes, the minimum number of BCLKs per ADCLRC period is 2
times the selected word length. ADCLRC must be high for a minimum of word length BCLKs and
low for a minimum of word length BCLKs. Any mark to space ratio on ADCLRC is acceptable
provided the above requirements are met.
PP Rev 1.0 June 2002
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
