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WM8773
The ADC data may also be output in DSP early or late modes, with ADCLRC used as a frame sync
to identify the MSB of the first word. The minimum number of BCLKs per ADCLRC period is 2 times
the selected word length
LEFT JUSTIFIED MODE
In left justified mode, the MSB of the ADC data is output on DOUT and changes on the same falling
edge of BCLK as ADCLRC and may be sampled on the rising edge of BCLK. ADCLRC is high
during the left samples and low during the right samples (Figure 9).
1/fs
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
DOUT
1
2
3
n
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
Figure 9 Left Justified Mode TIming Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB of the ADC data is output on DOUT and changes on the
falling edge of BCLK preceding an ADCLRC transition and may be sampled on the rising
edge of BCLK. ADCLRC is high during the left samples and low during the right samples).
1/fs
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
1
2
3
n
1
2
3
n
DOUT
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 10 Right Justified Mode TIming Diagram
PP Rev 1.0 June 2002
15
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
