WM8773
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MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK Duty cycle
tMCLKH
tMCLKL
tMCLKY
11
11
ns
ns
ns
28
40:60
60:40
Table 1 Master Clock Timing Requirements
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
DSP/
WM8773
ADC
ENCODER/
ADCLRC
DOUT
DECODER
Figure 2 Audio Interface - Master Mode
PP Rev 1.0 June 2002
8
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
