WM8770
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
00110
6:0
L4A[6:0]
1111111
(0dB)
0
Attenuation data for Left channel DACL4 in 1dB steps. See Table 11
Analogue
Attenuation
DACL4
7
8
L4ZCEN
UPDATE
DACL4 zero cross detect enable
0: zero cross disabled
1: zero cross enabled
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store L4A in intermediate latch (no change to output)
1: Store L4A and update attenuation on all channels.
00111
6:0
7
R4A[6:0]
R4ZCEN
1111111
(0dB)
0
Attenuation data for Right channel DACL4 in 1dB steps. See Table
11
Analogue
Attenuation
DACR4
DACR4 zero cross detect enable
0: zero cross disabled
1: zero cross enabled
8
UPDATE
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store R4A in intermediate latch (no change to output)
1: Store R4A and update attenuation on all channels.
Attenuation data for all channel DAC in 1dB steps. See Table 11
01000
6:0
7
MASTA[6:0]
MZCEN
1111111
(0dB)
0
Master
Analogue
Master zero cross detect enable
Attenuation
0: zero cross disabled
(all channels)
1: zero cross enabled
8
UPDATE
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store gain in intermediate latch (no change to output)
1: Store gain and update attenuation on all channels.
Table 10 Attenuation Register Map
Each DAC channel volume can be controlled digitally in an analogue volume stage after the DAC.
Attenuation is 0dB by default but can be set between 0 and –100dB in 1dB steps using the 7
Attenuation control words. All attenuation registers are double latched allowing new values to be pre-
latched to several channels before being updated synchronously. Setting the UPDATE bit on any
attenuation write will cause all pre-latched values to be immediately applied to the DAC channels. A
master attenuation register is also included, allowing all volume levels to be set to the same value in
a single write.
Note: The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-
latch but not applied to the relevant DAC. If UPDATE=1, all pre-latched values will be applied from
the next input sample. Writing to MASTA[6:0] overwrites any values previously sent to L1A[6:0],
L2A[6:0], L3A[6:0], L4A[6:0], R1A[6:0], R2A[6:0], R3A[6:0], R4A[6:0].
In addition a zero cross detect circuit is provided for each DAC volume under the control of bit 7
(xZCEN) in each DAC attenuation register. When ZCEN is set the attenuation values are only
updated when the input signal to the gain stage is close to the analogue ground level. This minimises
audible clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which
will generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of
12.288MHz). The timeout clock may be disabled by setting TOD.
REGISTER ADDRESS
10011
BIT
LABEL
DEFAULT
DESCRIPTION
3
TOD
0
DAC Analogue Zero cross detect
timeout disable
Timeout Clock Disable
0 : Timeout enabled
1: Timeout disabled
PD Rev 4.1 June 2005
32
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
