Production Data
WM8770
DAC OUTPUT PHASE
The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
10010
7:0
PH[7:0]
00000000
Bit
0
DAC
Phase
DAC Phase
DAC1L
DAC1R
1 = invert
1 = invert
1 = invert
1 = invert
1 = invert
1 = invert
1 = invert
1 = invert
1
2
3
4
5
6
7
DAC2L
DAC2R
DAC3L
DAC3R
DAC4L
DAC4R
ADC GAIN CONTROL
Control bits LAG[4:0] and RAG[4:0] control the ADC input gain, allowing the user to attenuate the
ADC input signal to match the full-scale range of the ADC. The gain is independently adjustable on
left and right inputs. Left and right inputs may also be independently muted. The LRBOTH control bit
allows the user to write the same attenuation value to both left and right volume control registers. The
ADC volume and mute also applies to the bypass signal path.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
11001
4:0
LAG[4:0]
01100
(0dB)
0
Attenuation data for Left channel ADC gain in 1dB steps. See Table
13
Attenuation
ADCL
5
MUTE
Mute for Left channel ADC:
0: Mute off
1: Mute on
6
LRBOTH
RAG[4:0]
0
Setting LRBOTH will write the same gain value to LAG[4:0] and
RAG[4:0]
11010
4:0
01100
(0dB)
0
Attenuation data for right channel ADC gain in 1dB steps. See Table
13
Attenuation
ADCR
5
6
MUTE
Mute for RIght channel ADC:
0: Mute off
1: Mute on
LRBOTH
0
Setting LRBOTH will write the same gain value to RAG[4:0] and
LAG[4:0]
ADC INPUT GAIN
Registers LAG and RAG control the left and right channel gain into the stereo ADC in 1dB steps from
+19dB to –12dB Table 8 shows how the attenuation levels are selected from the 5-bit words.
L/RAG[6:0]
ATTENUATION LEVEL
0
-12dB
:
:
0dB
:
01100
:
11111
+19dB
Table 13 ADC Gain Control
PD Rev 4.1 June 2005
35
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
