WM8770
Production Data
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
0.001
0.002
0.003
0.004
0.005
0.006
Time(s)
Figure 24 Application and Release of Soft Mute
Figure 24 shows the application and release of MUTE whilst a full amplitude sinusoid is being played
at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to
decay exponentially from the DC level of the last input sample. The output will decay towards VMID
with a time constant of approximately 64 input samples. If MUTE is applied to all channels for 1024
or more input samples the DAC will be muted if IZD is set. When MUTE is de-asserted, the output
will restart immediately from the current input sample.
Note that all other means of muting the DAC channels: setting the PL[3:0] bits to 0, setting the
PDWN bit or setting attenuation to 0 will cause much more abrupt muting of the output.
Each ADC channel also has an individual mute control bit, which mutes the input to the ADC. In
addition both channels may be muted by setting ADCMUTE.
REGISTER ADDRESS
11001
BIT
LABEL
DEFAULT
DESCRIPTION
ADC MUTE Left and Right
0 : Normal Operation
7
ADCMUTE
0
ADC Mute
1: mute ADC left and ADC
right
11001
5
5
MUTE
MUTE
0
0
ADC Mute select
0 : Normal Operation
1: mute ADC left
ADC Mute select
0 : Normal Operation
1: mute ADC right
ADC Mute Left
11010
ADC Mute Right
The Record outputs may be enabled by setting RECEN, where RECEN enables the REC1L and
REC1R outputs.
REGISTER ADDRESS
10100
BIT
LABEL
DEFAULT
DESCRIPTION
REC Output Enable
5
RECEN
0
Mute Control
0 : REC output muted
1: REC output enabled
PD Rev 4.1 June 2005
28
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
