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WM8770SIFV 参数 Datasheet PDF下载

WM8770SIFV图片预览
型号: WM8770SIFV
PDF下载: 下载PDF文件 查看货源
内容描述: 24位, 192kHz的8声道编解码器,带有音量控制 [24-bit, 192kHz 8-Channel Codec with Volume Control]
分类和应用: 解码器编解码器
文件页数/大小: 52 页 / 555 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8770  
Production Data  
ADC HIGHPASS FILTER DISABLE  
The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled  
using software control bit ADCHPD.  
REGISTER ADDRESS  
10110  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
ADC Highpass filter disable:  
0: Highpass filter enabled  
1: Highpass filter disabled  
8
ADCHPD  
0
ADC control  
ADC INPUT MUX AND POWERDOWN CONTROL  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
11011  
2:0  
LMX[2:0]  
000  
ADC left channel input mux control  
bits (see Table 14)  
ADC Mux and  
Powerdown  
Control  
6:4  
8
RMX[2:0]  
AINPD  
000  
1
ADC right channel input mux  
control bits (see Table 14)  
Input mux and buffer powerdown  
0: Input mux and buffer  
enabled  
1: Input mux and buffer  
powered down  
Register bits LMX and RMX control the left and right channel inputs into the stereo ADC. The default  
is AIN1. However if the analogue input buffer is powered down, by setting AINPD, then all 8-channel  
mux inputs are switched to buffered VMIDADC.  
LMX[2:0]  
LEFT ADC INPUT  
RMX[2:0]  
RIGHT ADC INPUT  
000  
001  
010  
011  
100  
101  
110  
111  
AIN1L  
AIN2L  
AIN3L  
AIN4L  
AIN5L  
AIN6L  
AIN7L  
AIN8L  
000  
001  
010  
011  
100  
101  
110  
111  
AIN1R  
AIN2R  
AIN3R  
AIN4R  
AIN5R  
AIN6R  
AIN7R  
AIN8R  
Table 14 ADC Input Mux Control  
OUTPUT SELECT AND ENABLE CONTROL  
Register bits MX1 to MX4 control the output select. The output select block consists of a summing  
stage and an input select switch for each input allowing each signal to be output individually or  
summed with other signals and output on each analogue output. The default for all outputs is DAC  
playback only. VOUT1/2/3 may be selected to output DAC playback, AUX, analogue bypass or a  
sum of these using the output select controls MX1/2/3[2:0]. VOUT4 may be selected to output DAC  
playback, analogue bypass or a sum of these signals using MX4[1:0]. It is recommended that bypass  
is not selected for output on more than two stereo channels simultaneously to avoid overloading the  
input buffer, resulting in a decrease in performance.  
The output mixers and EVRs can be powered down under control of OUTPD[3:0]. Each stereo  
channel may be powered down separately. Setting OUTPD[3:0] will power off the mixer and EVR and  
switch the analogue outputs VOUTL/R to VMIDDAC to maintain a dc level on the output.  
When setting OUTPD MX1/2/3/4 should be set to deselect all signals.  
PD Rev 4.1 June 2005  
36  
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