WM8770
Production Data
INFINITE ZERO DETECT ENABLE
Setting the IZD register bit will enable the internal infinite zero detect function:
REGISTER ADDRESS
10011
BIT
LABEL
DEFAULT
DESCRIPTION
2
IZD
0
Infinite zero Mute Enable
0 : disable inifinite zero mute
1: enable infinite zero Mute
DAC Channel Control
With IZD enabled, applying 1024 consecutive zero input samples to all 8 DAC channels will cause all
DAC outputs to be muted. Mute will be removed as soon as any channel receives a non-zero input.
ZERO FLAG OUTPUT
The DZFM control bits allow the selection of the eight DAC channel zero flag bits for output on the
ZFLAG1 and ZFLAG2 pins. A ‘1’ on ZFLAG1 or ZFLAG2 indicates 1024 consecutive zero input
samples to the channels selected.
REGISTER ADDRESS
10101
BIT
LABEL
DEFAULT
DESCRIPTION
7:4
DZFM[3:0]
0000
Selects the ouput for ZFLAG1
and ZFLAG2 pins (see Table 9).
A ‘1’ indicates 1024 consecutive
zero input samples on the
channels selected.
Zero Flag Select
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are
applied to the left and right DACs:
REGISTER ADDRESS
10011
BIT
LABEL
DEFAULT
DESCRIPTION
7:4
PL[3:0]
1001
PL[3:0]
Left
Right
Output
Output
DAC Control
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Mute
Left
Mute
Mute
Mute
Mute
Left
Right
(L+R)/2
Mute
Left
Left
Right
(L+R)/2
Mute
Left
Left
Left
Right
Right
Right
Right
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
Right
(L+R)/2
Mute
Left
Right
(L+R)/2
PD Rev 4.1 June 2005
30
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
