Production Data
WM8352
24.3.6 GPIO INTERRUPTS
The first-level GP_INT interrupt comprises several second-level interrupts for the 13 GPIO pins. Each
of these has a status bit in Register R30 and a mask bit in Register R35, as defined in Table 148.
ADDRESS
BIT
LABEL
GP12_EINT
DESCRIPTION
GPIO12 interrupt.
R30 (1Eh)
12
GPIO Interrupt
Status
(Trigger controlled by GP12 registers.)
Note: This bit is cleared once read.
GPIO11 interrupt.
11
10
9
GP11_EINT
GP10_EINT
GP9_EINT
GP8_EINT
GP7_EINT
GP6_EINT
GP5_EINT
GP4_EINT
GP3_EINT
GP2_EINT
GP1_EINT
GP0_EINT
(Trigger controlled by GP11 registers.)
Note: This bit is cleared once read.
GPIO10 interrupt.
(Trigger controlled by GP10 registers.)
Note: This bit is cleared once read.
GPIO9 interrupt.
(Trigger controlled by GP9 registers.)
Note: This bit is cleared once read.
GPIO8 interrupt.
8
(Trigger controlled by GP8 registers.)
Note: This bit is cleared once read.
GPIO7 interrupt.
7
(Trigger controlled by GP7 registers.)
Note: This bit is cleared once read.
GPIO6 interrupt.
6
(Trigger controlled by GP6 registers.)
Note: This bit is cleared once read.
GPIO5 interrupt.
5
(Trigger controlled by GP5 registers.)
Note: This bit is cleared once read.
GPIO4 interrupt.
4
(Trigger controlled by GP4 registers.)
Note: This bit is cleared once read.
GPIO3 interrupt.
3
(Trigger controlled by GP3 registers.)
Note: This bit is cleared once read.
GPIO2 interrupt.
2
(Trigger controlled by GP2 registers.)
Note: This bit is cleared once read.
GPIO1 interrupt.
1
(Trigger controlled by GP1 registers.)
Note: This bit is cleared once read.
GPIO0 interrupt.
0
(Trigger controlled by GP0 registers.)
Note: This bit is cleared once read.
R38 (26h)
12:0
“IM_” + name of respective bit Interrupt mask.
in R30
GPIO Interrupt
Mask
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R38 enables or masks the
corresponding bit in R30. The default
value for these bits is 0 (unmasked).
Table 148 GPIO Interrupts
PD, February 2011, Rev 4.4
203
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
