WM8352
Production Data
24.3.4 EXTERNAL INTERRUPTS
The first-level EXT_INT interrupt comprises three second-level interrupts for USB, Wall and Battery
supply status. Each of these has a status bit in Register R31 and a mask bit in Register R37, as
defined in Table 146. These flags are triggered on the rising and falling edges of the interrupt events.
ADDRESS
BIT
LABEL
DESCRIPTION
R31 (1Fh)
15
EXT_USB_FB_EINT
USB_FB changed interrupt.
Comparator
Interrupt Status
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
WALL_FB changed interrupt.
14
13
EXT_WALL_FB_EINT
EXT_BATT_FB_EINT
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
BATT_FB changed interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
R39 (27h)
15:13
“IM_” + name of respective bit Interrupt mask.
in R31
Comparator
Interrupt Status
Mask
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R39 enables or masks the
corresponding bit in R31. The default
value for these bits is 0 (unmasked).
Table 146 External Interrupts
24.3.5 CODEC INTERRUPTS
The first-level CODEC_INT interrupt comprises four second-level interrupts for the CODEC. Each of
these has a status bit in Register R31 and a mask bit in Register R39, as defined in Table 147.
These flags are triggered on the rising and falling edges of the interrupt events.
ADDRESS
BIT
LABEL
DESCRIPTION
Left channel Jack detection interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
Right channel Jack detection interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
Mic short-circuit detect interrupt.
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
Mic detect interrupt.
R31 (1Fh)
11
CODEC_JCK_DET_L_EINT
Comparator
Interrupt
Status
10
9
CODEC_JCK_DET_R_EINT
CODEC_MICSCD_EINT
CODEC_MICD_EINT
8
(Rising and Falling Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
R39 (27h)
11:8
“IM_” + name of respective
bit in R31
Comparator
Interrupt
Status Mask
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R39 enables or masks the
corresponding bit in R31. The default
value for these bits is 0 (unmasked).
Table 147 CODEC Interrupts
PD, February 2011, Rev 4.4
202
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
