Production Data
WM8352
24.3.12 WAKE-UP INTERRUPTS
The first-level WKUP_INT interrupt comprises several second-level interrupts. After a system reset,
these indicate to the host processor why the reset occurred. Each wake-up interrupt has a status bit
in Register R31 and a mask bit in Register R30, as defined in Table 154.
ADDRESS
BIT
LABEL
DESCRIPTION
R31 (1Fh)
6
WKUP_OFF_STATE_EINT
Indicates that the chip started from the
OFF state.
Comparator
Interrupt
Status
(Rising Edge triggered)
Note: This bit is cleared once read.
5
4
WKUP_HIB_STATE_EINT
WKUP_CONV_FAULT_EINT
Indicated the chip started up from the
hibernate state.
(Rising Edge triggered)
Note: This bit is cleared once read.
Indicates the wakeup was caused by a
converter fault leading to the chip being
reset.
(Rising Edge triggered)
Note: This bit is cleared once read.
3
2
WKUP_WDOG_RST_EINT
WKUP_GP_PWR_ON_EINT
Indicates the wakeup was caused by a
watchdog heartbeat being missed, and
hence the chip being reset.
(Rising Edge triggered)
Note: This bit is cleared once read.
PWR_ON (Alternate GPIO function) pin
has been pressed for longer than
specified time.
(Rising Edge triggered)
Note: This bit is cleared once read.
1
0
WKUP_ONKEY_EINT
ON key has been pressed for longer than
specified time.
(Rising Edge triggered)
Note: This bit is cleared once read.
WKUP_GP_WAKEUP_EINT
WAKEUP (Alternate GPIO function) pin
has been pressed for longer than
specified time.
(Rising Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
R39 (27h)
6:0
“IM_” + name of respective
bit in R31
Comparator
Interrupt
Status Mask
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R39 enables or masks the
corresponding bit in R31. The default
value for these bits is 0 (unmasked).
Table 154 Wake-up Interrupts
PD, February 2011, Rev 4.4
207
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
