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W9825G6KH-6 参数 Datasheet PDF下载

W9825G6KH-6图片预览
型号: W9825G6KH-6
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 16MX16, 5ns, CMOS, PDSO54, TSOP2-54]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 42 页 / 714 K
品牌: WINBOND [ WINBOND ]
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W9825G6KH  
7.17 Power Down Mode  
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are  
gated off to reduce the power. The Power Down mode does not perform any refresh operations,  
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the  
device.  
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation  
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be  
enabled with CKE held high for a period equal to tCKS (min) + tCK (min).  
7.18 No Operation Command  
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to  
prevent the SDRAM from registering any unwanted commands between operations. A No Operation  
Command is registered when CS is low with RAS  
,
CAS and WE held high at the rising edge of  
the clock. A No Operation Command will not terminate a previous operation that is still executing, such  
as a burst read or write cycle.  
7.19 Deselect Command  
The Deselect Command performs the same function as a No Operation Command. Deselect  
Command occurs when CS is brought high, the RAS  
cares.  
,
CAS and WE signals become don't  
7.20 Clock Suspend Mode  
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low  
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode  
deactivates the internal clock and suspends any clocked operation that was currently being executed.  
There is a one clock delay between the registration of CKE low and the time at which the SDRAM  
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are  
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay  
from when CKE returns high to when Clock Suspend mode is exited.  
Publication Release Date: Sep. 01, 2014  
Revision: A02  
- 11 -  
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