W90N745CD/W90N745CDG
6.15.2 USI Registers Map
R: read only, W: write only, R/W: both read and write
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
0x0000_0004
0x0000_0000
0x0000_0000
N/A
USI_CNTRL
0xFFF8_6200 R/W Control and Status Register
USI_DIVIDER 0xFFF8_6204 R/W Clock Divider Register
USI_SSR
Reserved
USI_Rx0
USI_Rx1
USI_Rx2
USI_Rx3
USI_Tx0
USI_Tx1
USI_Tx2
USI_Tx3
0xFFF8_6208 R/W Slave Select Register
0xFFF8_620C N/A Reserved
0xFFF8_6210
0xFFF8_6214
0xFFF8_6218
0xFFF8_621C
0xFFF8_6210
0xFFF8_6214
0xFFF8_6218
0xFFF8_621C
R
R
Data Receive Register 0
Data Receive Register 1
Data Receive Register 2
Data Receive Register 3
Data Transmit Register 0
Data Transmit Register 1
Data Transmit Register 2
Data Transmit Register 3
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
R
R
W
W
W
W
NOTE 1: When software programs CNTRL, the GO_BUSY bit should be written last.
Publication Release Date: September 22, 2006
Revision A2
- 351 -
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