W90N745CD/W90N745CDG
USI Divider Register (USI_DIVIDER)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
USI_Divider 0xFFF8_6204 R/W USI Clock Divider Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
27
19
11
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
DIVIDER[15:8]
4
3
1
0
DIVIDER[7:0]
BITS
DESCRIPTIONS
Clock Divider Register
The value in this field is the frequency divider of the system clock pclk
to generate the serial clock on the output mw_sclk_o. The desired
frequency is obtained according to the following equation:
[15:0]
DIVIDER
f pclk
fsclk
=
(
DIVIDER +1 *2
)
NOTE: Suggest DIVIDER should be at least 1.
- 354 -
WINBOND [ WINBOND ]
