W90N745CD/W90N745CDG
I2C Data Receive Register 0/1 (I2C_RxR 0/1)
REGISTER
OFFSET
R/W
R
DESCRIPTION
I2C Data Receive Register 0
I2C Data Receive Register 1
RESET VALUE
0x0000_0000
0x0000_0000
I2C_RXR0 0xFFF8_6010
I2C_RXR1 0xFFF8_6110
R
31
23
15
7
30
22
14
6
29
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
21
13
5
Reserved
Rx[7:0]
1
0
BITS
DESCRIPTIONS
[31:8]
Reserved
Rx
Reserved
Data Receive Register
The last byte received via I2C bus will put on this register. The I2C core
only used 8-bit receive buffer.
[7:0]
Publication Release Date: September 22, 2006
- 347 -
Revision A2
WINBOND [ WINBOND ]
