W90N745CD/W90N745CDG
6.15 Universal Serial Interface
The USI is a synchronous serial interface performs a serial-to-parallel conversion on data characters
received from the peripheral, and a parallel-to-serial conversion on data characters received from
CPU. It can generate an interrupt signal when data transfer is finished and can be cleared by writing 1
to the interrupt flag. The active level of device/slave select signal can be chosen to low active or high
active, which depends on the peripheral it’s connected. Writing a divisor into DIVIDER register can
program the frequency of serial clock output. This master core contains four 32-bit transmit/receive
buffers, and can provide burst mode operation. The maximum bits can be transmitted/received is 32
bits, and can transmit/receive data up to four times successive.
The USI (Microwire/SPI) Master Core includes the following features:
• AMBA APB interface compatible
• Support USI (Microwire/SPI) master mode
• Full duplex synchronous serial data transfer
• Variable length of transfer word up to 32 bits
• Provide burst mode operation, transmit/receive can be executed up to four times in one transfer
• MSB or LSB first data transfer
• Rx and Tx on both rising or falling edge of serial clock independently
• 1 slave/device select lines
• Fully static synchronous design with one clock domain
Publication Release Date: September 22, 2006
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Revision A2
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