W90N745CD/W90N745CDG
Continued
BITS
DESCRIPTION
Enable nIRQ2
Setting this bit 1 to enable nIRQ2
1 = Enable nIRQ2
[3]
[2]
EnIRQ2
0 = Disable nIRQ2
The AIC interrupt channel 31 is reserved for nIRQ3 and nIRQ2 (wire-OR),
if this bit is set and nIRQ2 occur, then it will send an interrupt request
signal into AIC module.
Debounce circuit enable for nIRQ2
(alternative function of GPIO0 pin)
1 = Enable debounce
DBE2
0 = Disable debounce
The nIRQ2 shares the same debounce circuit with nIRQ[1:0], software can
configure debounce sampling time in GPIO_DEBNCE control register.
DBE2 function is the same as DBE0 in GPIO_DBENCE register.
nIRQ2 source type
ISTYPE2
2’b00
Interrupt Source Type
LOW level sensitive
[1:0]
ISTYPE2
2’b01
HIGH level sensitive
Negative edge triggered
Positive edge triggered
2’b10
2’b11
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