欢迎访问ic37.com |
会员登录 免费注册
发布采购

W90N745CDG 参数 Datasheet PDF下载

W90N745CDG图片预览
型号: W90N745CDG
PDF下载: 下载PDF文件 查看货源
内容描述: 16位/ 32位ARM微控制器 [16/32-bit ARM microcontroller]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 422 页 / 2455 K
品牌: WINBOND [ WINBOND ]
 浏览型号W90N745CDG的Datasheet PDF文件第339页浏览型号W90N745CDG的Datasheet PDF文件第340页浏览型号W90N745CDG的Datasheet PDF文件第341页浏览型号W90N745CDG的Datasheet PDF文件第342页浏览型号W90N745CDG的Datasheet PDF文件第344页浏览型号W90N745CDG的Datasheet PDF文件第345页浏览型号W90N745CDG的Datasheet PDF文件第346页浏览型号W90N745CDG的Datasheet PDF文件第347页  
W90N745CD/W90N745CDG  
6.14 I2C Interface  
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange  
between devices. The I2C standard is a true multi-master bus including collision detection and  
arbitration that prevents data corruption if two or more masters attempt to control the bus  
simultaneously.  
Serial, 8-bit oriented bi-directional data transfers can be made up to 100 kbit/s in Standard-mode, up  
to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode. Only 100kbps and  
400kbps modes are supported directly. For High-speed mode special IOs are needed. If these IOs are  
available and used, then High-speed mode is also supported.  
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-  
by-byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the  
MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled  
during the high period of SCL; therefore, the SDA line may be changed only during the low period of  
SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is  
high is interpreted as a command (START or STOP).  
The I2C Master Core includes the following features:  
AMBA APB interface compatible  
Compatible with Philips I2C standard, support master mode  
Multi Master Operation  
Clock stretching and wait state generation  
Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer  
Software programmable acknowledge bit  
Arbitration lost interrupt, with automatic transfer cancellation  
Start/Stop/Repeated Start/Acknowledge generation  
Start/Stop/Repeated Start detection  
Bus busy detection  
Supports 7 bit addressing mode  
Fully static synchronous design with one clock domain  
Software mode I2C  
- 338 -  
 
 复制成功!