W90N745CD/W90N745CDG
GPIO Interrupt Configuration Register (GPIO_XICFG)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
GPIO_XICFG
0xFFF8_3074
R/W
Extend interrupt configure register 0xXXXX_XX00
31
23
15
30
22
14
6
29
21
13
5
28
27
19
26
18
10
25
17
9
24
16
8
RESERVED
20
RESERVED
12
11
RESERVED
7
4
3
2
1
0
EnIRQ3
DBE3
ISTYPE3
EnIRQ2
DBE2
ISTYPE2
BITS
DESCRIPTION
[31:8]
RESERVED
-
Enable nIRQ3
Setting this bit 1 to enable nIRQ3.
1 = Enable nIRQ3
[7]
EnIRQ3
0 = Disable nIRQ3
The AIC interrupt channel 31 is reserved for nIRQ3 and nIRQ2 (wired-OR),
if this bit is set and nIRQ3 occur, then it will send an interrupt request
signal into AIC module.
Debounce circuit enable for nIRQ3
(alternative function of nWAIT pin)
The nIRQ3 shares the same debounce circuit with nIRQ[3:0], software can
configure debounce sampling time in GPIO_DEBNCE control register.
DBE3 function is the same as DBE0 in GPIO_DBENCE register.
[6]
DBE3
1 = Enable debounce
0 = Disable debounce
nIRQ3 source type
ISTYPE3
2’b00
Interrupt Source Type
LOW level sensitive
[5:4]
ISTYPE3
2’b01
HIGH level sensitive
Negative edge triggered
Positive edge triggered
2’b10
2’b11
Publication Release Date: September 22, 2006
Revision A2
- 335 -
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