W90N745CD/W90N745CDG
Timer Interrupt Status Register (TISR)
REGISTER
TISR
ADDRESS
R/W
DESCRIPTION
RESET VALUE
0xFFF8_1018 R/W Timer Interrupt Status Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
Reserved
19
Reserved
11
Reserved
26
18
10
2
25
17
9
24
16
8
3
1
0
Reserved
TIF1
TIF0
BITS
DESCRIPTIONS
Timer Interrupt Flag 1
This bit indicates the interrupt status of Timer channel 1.
0 = It indicates that the Timer 1 dose not countdown to zero yet.
[1]
TIF1
TIF0
1 = It indicates that the counter of Timer 1 has decremented to zero.
The interrupt flag is set if it was enable.
NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
Timer Interrupt Flag 0
This bit indicates the interrupt status of Timer channel 0.
0 = It indicates that the Timer 0 dose not countdown to zero yet.
[0]
1 = It indicates that the counter of Timer 0 has decremented to zero.
The interrupt flag is set if it was enable.
NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
Watchdog Timer Control Register (WTCR)
REGISTER
WTCR
ADDRESS
R/W
DESCRIPTION
RESET VALUE
0xFFF8_101C R/W Watchdog Timer Control Register
0x0000_0400
Publication Release Date: September 22, 2006
Revision A2
- 293 -
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