W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:5]
Reserved
-
ICE debug mode acknowledge enable
0 = When DBGACK is high, the UART receiver time-out clock will be
held
[4]
nDBGACK_EN
1 = No matter what DBGACK is high or not, the UART receiver timer-
out clock will not be held
MODEM Status Interrupt (Irpt_MOS) Enable
0 = Mask off Irpt_MOS
1 = Enable Irpt_MOS
[3]
[2]
[1]
MSIE
RLSIE
THREIE
Receive Line Status Interrupt (Irpt_RLS) Enable
0 = Mask off Irpt_RLS
1 = Enable Irpt_RLS
Transmit Holding Register Empty Interrupt (Irpt_THRE) Enable
0 = Mask off Irpt_THRE
1 = Enable Irpt_THRE
Receive Data Available Interrupt (Irpt_RDA) Enable and
Time-out Interrupt (Irpt_TOUT) Enable
0 = Mask off Irpt_RDA and Irpt_TOUT
[0]
RDAIE
1 = Enable Irpt_RDA and Irpt_TOUT
HSUART Divider Latch (Low Byte) Register (HSUART_DLL)
REGISTER
OFFSET
R/W
DESCRIPTION
RESET VALUE
0x00
R/W
Divisor Latch Register (LS) (DLAB = 1)
0x0000_0000
HSUART_DLL
31
23
15
7
30
29
21
13
5
28
Reserved
20
Reserved
12
Reserved
27
19
11
3
26
18
10
2
25
17
9
24
16
8
22
14
6
4
1
0
Baud Rate Divider (Low Byte)
Publication Release Date: September 22, 2006
Revision A2
- 277 -
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